AWG G3 PAD FOR PS3 Spécifications télécharger pdf (Page 14)

List Of Figures

14 System Reference, January 2001

Figure 96 Example for Using Loop Back Route 213

Figure 97 Coherent Sampling 217

Figure 98 Sampler Block Diagram 219

Figure 99 DC Routes 221

Figure 100 Loop Back Routes 222

Figure 101 TIA Measurement Functions 226

Figure 102 TrigDelayCnt Parameters for Period/Frequency Measurement 227

Figure 103 TrigDelayCnt Parameters for Pulse Width Measurement 228

Figure 104 TrigDelayCnt Parameters for Propagation Delay Measurement 229

Figure 105 Examples of Trigger Modes 231

Figure 106 trigMode and trigEdge 232

Figure 107 Measuring Multiple Intervals 233

Figure 108 Front-end Module and TIA Instrument 236

Figure 109 Front-end Module Block Diagram 237

Figure 110 Input Block 238

Figure 111 TIA Instrument Block Diagram 241

Figure 112 Start Timing of Analog Module after Receiving Trigger 244

Figure 113 Delay Factors for Analog Module Operation 245

Figure 114 Timing Chart and Delay Factor 246

Figure 115 Synchronization Trigger 248

Figure 116 Adjusting Synchronization Timing (1) 249

Figure 117 Adjusting Synchronization Timing (2) at Analog Module Pogo Pin

251

Figure 118 Adjusting Synchronization Timing (3) at DUT Pin for AWG 252

Figure 119 Adjusting Synchronization Timing (4) at DUT Pin for Dig itizer and Sampler

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Figure 120 Trigger Signal Edge Placement when TRGL Is Set to Trigger Line Length

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Figure 121 Trigger Signal Edge Placement when TRGL Is Set to Zero 257

Figure 122 Trigger Signal Edge Placement when TRGL Is Set to Trigger Line Length

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Figure 123 Trigger Signal Edge Placement when TRGL Is Set to Zero 259

Figure 124 “Master-Slave” Internal Connections 261

Figure 125 Examples of Definition of Master/Slave Modules 262

Figure 126 Master Trigger Function 263

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AWG G3 PAD FOR PS3 Spécifications Page 14