
Master Clock System 3 Hardware Components
System Reference, January 2001
51
For the master clock generator on the clock board,
Note that there are some restrictions about maximum
resolution that can be programmed on the software for
digital channels using fixed timing. You can avoid them if
timing equations are used.
Master Clock Distribution In the case of a single master clock, the master clock of the
digital clock domain is used for both digital channel
boards and analog modules. The master clock generated
from the clock board in cardcage #1 on the 512-pin
testhead or #5 on the 1024-pin testhead or the digital clock
domain’s AMC is distributed around the ring of all boards
in other cardcages. Hence, both digital channel boards and
analog modules use the master clock of the digital clock
domain.
In the cage of two master clocks, the master clock of the
digital clock domain is used for all the digital channel
boards. The master clock generated from the clock board
in cardcage #1 on the 512-pin testhead or #5 on the 1024-
pin testhead or the digital clock domain’s AMC is distrib-
uted around the ring of all digital boards and some analog
modules in other cardcages.
For each analog module, you can select the desired clock
domain from the digital or analog clock domains. If you
select the master clock of the digital clock domain for an
analog module, the analog module uses the same master
clock used for the digital channel boards. That is, it uses
one master clock for both digital channel boards and
analog modules.
If you select the master clock of the analog clock domain,
the analog module uses the master clock generated from
the clock board in it’s own cardcage or the analog clock
domain’s AMC. This means it uses a different master clock
from the master clock of the digital clock domain.
Range: 2 - 5 ns (200 MHz - 500 MHz)
Max. Resolution: 15 digits (approx. 1 µHz)
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